The PGY-PCIeGen3/4/5 -PA is a PCIe Protocol Analyzer that supports protocol analysis up to PCIe Gen5 speeds. PCIe design and test engineers can easily captures and record traces at 2.5, 5.0, 8, 16 and 32GT/s at specific event and obtain error report instantaneously at affordable price. This enables the design and test engineers to reduce the development time and address the time to market needs. PCIe data is captured using interposers between the root complex and end point (Device under test). PCIe Gen3/4/5 Protocol Analyzer’s software provides complete decode and error analysis of Transaction Layer Packets (TLPs), Data Link Layer Packets (DLLPs) and with LTSSM information.
