Announcements
Prodigy launches PCIe Gen 6 Protocol Analyzer with 64 GT/s capture capability
During the power-on sequence of a PCI Express (PCIe) system, the reference clock (REFCLK) and sideband signals may not have reached their required stability or operating tolerance. The PERST# (PCIe Reset) signal is an active-low, open-drain output driven by the Root Complex (RC). It is used to hold the endpoint (EP) devices in reset while […]
UFS 4.0 in Automotive: Powering Next-Generation Vehicles In today’s rapidly evolving automotive landscape, vehicles are transforming into sophisticated, connected computing platforms. As manufacturers push the boundaries of safety, connectivity, and user experience, the need for high-performance storage solutions becomes paramount. Universal Flash Storage (UFS) 4.0 is emerging as a critical technology that meets these demands, […]
Understanding Clock Stretching in I²C Communication and How PGY-I2C-EX-PD Simplifies Debugging Efficient communication between devices is crucial in modern embedded systems, especially when using protocols like I²C (Inter-Integrated Circuit). One of the key mechanisms that ensures smooth data transfer between fast masters and slower slaves is clock stretching. This blog explores the importance of clock […]
Universal Flash Storage (UFS) uses the MIPI Alliance’s MPHY physical layer specification to interconnect the UFS device with the host (SoC) or application processor. This is an embedded interface with no connectors between the host and UFS device. In typical electronic systems, the MPHY signals are routed between PCB layers, making them inaccessible. However, test […]
DDR5 is fifth generation dynamic random-access memory provides superior performance over DDR4. It is designed for next generation CPUs and GPU to address artificial intelligence applications and large data processing applications with fast access to the data. One of the key features of the DDR5 is power management integrated circuit (PMIC), which regulates the is […]
Introduction The MIPI I3C Bus interface enhances the legacy I2C standard by reducing the number of physical pins required in sensor systems while supporting low-power, high-speed digital communication, similar to UART and SPI interfaces. This versatility allows for seamless integration with existing systems. I3C is essential for integrating sensors in smartphones, IoT devices, and wearables, […]
Overview In the realm of embedded systems, I2C (Inter-Integrated Circuit) is a widely used communication protocol that enables devices to communicate with each other over a short distance. One critical aspect of I2C communication is clock stretching, which allows slower devices to control the pace of communication by holding the clock line low. One of […]
UFS is becoming widely used storage device in many different applications smartphone, Tablets, Digital Cameras and Camcorders, Automotive, Augmented Reality and Virtual reality, wearable, augmented devices and hard disk drives. Now it expected to used in laptops in the near future. UFS stands for Universal Flash Storage. It is type of non-volatile memory which can […]
MCTP Over I3C in the PGY-I3C-EX-PD Overview of I3C MIPI I3C, or I3C, stands for the MIPI I3C (Sensor Interface) standard, which serves as a versatile and efficient interface for connecting sensors to application processors, microcontrollers, and other intelligent devices. I3C is designed to overcome limitations of traditional sensor interfaces like I2C and SPI by […]
串行存在检测（SPD）是一种自动获取 DDR3/4/5 内存模块信息的标准方法. 当一个系统接通电源时，它会通过识别不同的硬件组件开始自动配置系统。 串行存在检测（SPD）是 DDR3/4/5 中的一项功能，可使电子系统了解 DDR 内存的详细信息及其定时信息。 DDR3/4 内存模块使用 SM bus提供这个信息。 对于最新的超高速内存，DDR5 使用低压信号（1V）I3C 接口来读取内存详细信息及其定时信息。 Fig 1. 基于 DDR5 的系统设计中的典型 I3C 总线架构 典型的 I3C 总线结构如图 1 所示. 当主机控制器使用串行存在检测 – SPD5 集线器连接 DDR5 模块 在设计和测试阶段，使用示波器监控这种架构中的所有 I3C 总线是非常具有挑战性的。 调试这些设计的一些关键要求如下： 需要能在 1V 信号幅度下工作的逻辑分析仪。 需要可以同时获取不同的 I3C 逻辑活动。 需要可以对不同的速率运行的I3C总线进行解码，频率从 100KHz 到 12.5MHz 不等 监控 I3C 总线中的特定事件 Prodigy Technovations 在现有的逻辑分析仪上开发了业内首个多通道 […]
